1. Field of the Invention
The present invention relates generally to integrated circuits and fabrication methods, and more particularly to the formation of integrated circuits with insulation layers having low dielectric constants.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide.
A consequence of having of patterned conductive material separated by an insulating material, whether the conductive material is on a single level or multiple levels, is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, unnecessary power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to increase the distance between them. Increased spacing between interconnect lines has adverse consequences, such as increased area requirements and the corresponding increases in manufacturing costs. Another way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant.
What is needed is a structure providing low parasitic capacitance between patterned conductors, and methods of making such a structure.